? semiconductor components industries, llc, 2008 may, 2008 ? rev. 1 1 publication order number: NUP412VP5/d NUP412VP5 low capacitance quad array for esd protection this integrated transient voltage suppressor device (tvs) is designed for applications requiring transient overvoltage protection. it is intended to be used in sensitive equipment such as wireless headsets, pdas, digital cameras, computers, printers, communication systems, and other applications. the integrated design provides very effective and reliable protection for four separate lines using only one package. this device is ideal for situations where board space is at a premium. features ? esd protection: iec61000 ? 4 ? 2: level 4 ? four separate unidirectional configurations for protection ? low leakage current < 1 a @ 9 v ? small sot ? 953 smt package ? low capacitance ? these are pb ? free devices benefits ? provides protection for esd industry standards: iec 61000, hbm ? protects four lines against transient voltage conditions ? minimize power consumption of the system ? minimize pcb board space typical applications ? cellular and portable electronics ? serial and parallel ports ? microprocessor based equipment ? notebooks, desktops, servers sot ? 953 case 526ab 5 4 1 2 3 marking diagram http://onsemi.com device package shipping ? ordering information NUP412VP5t5g sot ? 953 (pb ? free) 8000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 2 = specific device code m = date & assembly code 2m 1
NUP412VP5 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current v br maximum temperature coefficient of v br i f forward current v f forward voltage @ i f z zt maximum zener impedance @ i zt i zk reverse current z zk maximum zener impedance @ i zk uni ? directional i pp i f v i i r i t v rwm v c v br v f maximum ratings (t a = 25 c unless otherwise noted) characteristic symbol value unit peak power dissipation (8 x 20 s @ t a = 25 c) (note 1) p pk 18 w thermal resistance junction ? to ? ambient above 25 c, derate r ja 560 4.5 c/w mw/ c maximum junction temperature t jmax 150 c operating junction and storage temperature range t j t stg ? 55 to +150 c lead solder temperature (10 seconds duration) t l 260 c human body model (hbm) machine model (mm) esd 8000 400 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. non ? repetitive current. electrical characteristics (t a = 25 c) device device marking breakdown voltage v br @ 5 ma (volts) leakage current i rm @ v rm typ capacitance @ 0 v bias (pf) (note 2) typ capacitance @ 3 v bias (pf) (note 2) min nom max v rwm i rwm ( a) typ max typ max NUP412VP5 (note 3) 2 11.4 12 12.7 9.0 0.5 6.5 10 3.5 5.0 2. capacitance of one diode at f = 1 mhz, t a = 25 c. 3. v br at 5 ma.
NUP412VP5 http://onsemi.com 3 typical electrical characteristics figure 1. reverse leakage versus temperature t, temperature ( c) i r , reverse leakage ( a) figure 2. capacitance bias voltage (v) typical capacitance (pf) 1 mhz frequency v f , forward voltage (v) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.1 0.01 0.001 1 i f , forward current (a) t a = 25 c figure 3. 8 20 s pulse waveform 100 90 80 70 60 50 40 30 20 10 0 020406080 t, time ( s) % of peak pulse current t r pulse width (t p ) is defined as that point where the peak current decay = 8 s half value i rsm /2 @ 20 s t p peak value i rsm @ 8 s figure 4. forward voltage figure 5. power derating curve t a , ambient temperature ( c) 150 125 100 75 50 25 0 90 80 70 60 50 40 30 20 10 0 100 110 % of rated power or i pp 0 0.0005 0.001 0.0015 0.002 0.0025 0.003 0.0035 ? 60 ? 40 ? 20 0 20 40 60 80 100 120 140 160 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
NUP412VP5 http://onsemi.com 4 package dimensions sot ? 953 case 527ab ? 01 issue b *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.35 0.014 0.20 0.08 0.90 0.0354 0.35 0.014 0.20 0.08 mm inches scale 20:1 e b e d c a l x 0.08 ? y ? ? x ? h e 5x y 12 3 4 5 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. dim min nom max millimeters a 0.34 0.42 0.50 b 0.10 0.15 0.20 c 0.05 0.10 0.15 d 0.95 1.00 1.05 e 0.75 0.80 0.85 e 0.35 bsc l 0.05 0.10 0.15 0.95 1.00 1.05 h e 0.013 0.017 0.020 0.004 0.006 0.008 0.002 0.004 0.006 0.037 0.039 0.041 0.03 0.032 0.034 0.014 bsc 0.002 0.004 0.006 0.037 0.039 0.041 min nom max inches on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NUP412VP5/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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